Methods of forming self-aligned contact structures in semiconductor integrated circuit devices

ABSTRACT

Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns. The first contact hole is then widened in a self-aligned manner using the capping insulating layer as an etch-stop layer. This widening step is performed by wet etching sidewalls of the first contact hole using an etchant that etches the upper interlayer insulating layer faster than the capping insulating layer. In this manner, the first contact hole may be formed to initially compensate for potential misalignment errors and then a self-aligned wet etching step may be performed to widen the first contact hole into a second contact hole so that low resistance contacts (e.g., contact plugs) can be provided therein.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.09/556,499, filed Apr. 24, 2000 now U.S. Pat. No. 6,649,508, which isrelated to Korean Application No. 2000-5358, filed Feb. 3, 2000, thedisclosures of which are hereby incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to integrated circuit device fabrication methodsand, more particularly, to methods of forming self-aligned contactstructures in semiconductor integrated circuit devices.

BACKGROUND OF THE INVENTION

Attempts to increase device integration density in microelectronicintegrated circuits have typically resulted in the fabrication ofsmaller and smaller devices that are spaced more closely together. Inorder to electrically access these devices, conventional techniques tophotolithographically define the location of contact holes to thesedevices have also had to improve. Such improvements have typicallyincluded the development of photolithographic alignment techniqueshaving reduced tolerances. Alternatively, attempts to reduce contacthole size may not represent an acceptable approach when forming highlyintegrated devices because reductions in contact hole size typicallylead to substantial and unacceptable increases in contact resistance.

Techniques to reduce photolithographic alignment tolerances havetypically not scaled at the same rate as techniques to scale the size ofmicroelectronic devices. To address this limitation associated withphotolithographic alignment, self-aligned contact hole fabricationtechniques that are less dependent on photolithographic accuracy havebeen developed.

A method of forming self-aligned contact holes is taught in U.S. Pat.No. 5,897,372 to Howard entitled “Formation of a self-aligned integratedcircuit structure using silicon-rich nitride as a protective layer”.According to the U.S. Pat. No. 5,897,372, a gate electrode surrounded byan upper protection layer and a side-wall spacer is formed on asemiconductor substrate. A thin silicon-rich silicon nitride layer and athick inter-layer insulating layer are sequentially formed on the entiresurface of the resultant structure. The inter-layer insulating layer andthe silicon-rich silicon nitride layer are dry-etched in sequence toform a self-aligned contact hole exposing the substrate between the gateelectrodes. Here, a width of the self-aligned contact hole is wider thana space between the gate electrodes in order to maximize the exposedarea of the substrate. Accordingly, an edge portion of the protectionlayer on the gate electrode is exposed by the self-aligned contact hole.At this time, in the event both the protection layer and the spacer areformed of a silicon oxide layer, the gate electrode may be exposed dueto the over etching during a dry-etching process for forming theself-aligned contact hole. Thus, in order to overcome the above problem,both the protection layer and the spacer should be formed of siliconnitride layer having etch selectivity with respect to the inter-layerinsulating layer or the thickness of the silicon-rich silicon nitridelayer should be increased. However, the silicon nitride layer and thesilicon-rich silicon nitride layer have higher dielectric constants thanthe silicon oxide layer. Therefore, the parasitic capacitance betweenthe interconnection filling the self-aligned contact hole and the gateelectrode is increased and such increase may degrade the electricalcharacteristics of the integrated circuit.

As a result, such self-aligned contact hole fabrication techniques maystill be prone to reliability problems when photolithographic alignmenttechniques having relatively large alignment tolerances are used. Thus,notwithstanding such self-alignment techniques, there continues to be aneed for improved methods of forming contact holes in highly integratedcircuit substrates.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide methods offorming self-aligned contact structure, which can minimize the parasiticcapacitance between two adjacent conductive layers and improve thereliability of the alignment techniques.

It is another object of the present invention to provide methods offorming self-aligned contact structure, which can minimize the contactresistance.

These and other objects, advantages and features of the presentinvention may be provided by methods of forming self-aligned contactstructure of integrated circuit devices (e.g., memory devices). Thesemethods improve process reliability by reducing the likelihood thatcontact holes will become misaligned to underlying integrated circuitdevice patterns and thereby potentially expose the patterns in anadverse manner. According to one embodiment of the present invention, amethod of forming self-aligned contact structure includes the steps offorming a plurality of interconnection patterns on a substrate and thencovering a surface of the interconnection patterns and a surface of thesubstrate with a capping insulating layer. The capping insulating layeris then covered with an upper inter-layer insulating layer filling gapregions between the interconnection patterns. The upper inter-layerinsulating layer and the capping insulating layer are then dry-etched insequence to form a narrow contact hole, e.g., a first contact hole thatexposes the substrate, but preferably does not expose theinterconnection patterns. In this embodiment, the capping insulatinglayer may be formed of silicon nitride layer. The first contact hole isthen widened in a self-aligned manner using the capping insulating layeras an etch-stop layer. In particular, the first contact hole is widenedto form a second contact hole exposing the capping insulating layer onthe sidewalls of the interconnection patterns, by wet etching sidewallsof the first contact hole using an etchant that etches the upperinter-layer insulating layer faster than the capping insulating layer.In this manner, the first contact hole may be formed to initiallycompensate for potential misalignment errors and then a self-aligned wetetching step may be performed to widen the first contact hole so thatlow resistance contacts (e.g., contact plugs) can be provided in thesecond contact hole. During this widening step, the selectivity of thewet etchant can be made high to reduce the likelihood that theinterconnection patterns will become exposed to the second contact hole.

According to another aspect of the present invention, the step offorming the second contact hole is preferably followed by the steps offorming an oxide spacer on a sidewall of the second contact hole andthen etching a protrusion of the capping insulating layer extendingopposite the substrate, using the oxide spacer as an etching mask. Thislatter sequence of steps is preferably performed in order to increasethe area of the substrate that is exposed by the second contact hole andthereby lower the contact resistance between a subsequently formedcontact plug and the substrate.

According to another embodiment of the present invention, a method offorming self-aligned contact structure of an integrated circuit memorydevice comprises the steps of forming a lower inter-layer insulatinglayer on a semiconductor substrate and then forming a pad contact holein the lower inter-layer insulating layer. A pad plug is then formed inthe pad contact hole using conventional techniques. First and second bitline patterns are then formed at adjacent locations on an upper surfaceof the lower inter-layer insulating layer. A capping insulating layerthat covers the pad plug and the first and second bit line patterns isthen deposited. An upper interlayer insulating layer is then formed onthe capping insulating layer. The upper interlayer insulating layer andthe capping insulating layer are then etched in sequence to form a firstcontact hole that exposes a first portion of the underlying pad plug.The first contact hole is then widened in a preferred self-alignedmanner by selectively etching the sidewalls of the first contact holewith an etchant that etches the upper interlayer insulating layer at afaster rate than the capping insulating layer, thereby forming a secondcontact hole exposing the capping insulating layer on the sidewalls ofthe bit line patterns. Next, an oxide spacer is formed on the sidewallof the second contact hole. After the oxide spacer has been formed, thecapping insulating layer is again etched to expose a second portion ofthe pad plug that is greater than the first portion. This step ispreferably performed using the oxide spacer as an etching mask.Alternatively, the oxide spacer may be formed with an etching processshowing a poor etch selectivity respect to the capping insulating layerso that the capping insulating layer is etched concurrently with theformation of the oxide spacer. In this case, it is not required toadditionally etch the capping insulating layer with an extra etchingprocess. The second contact hole is then filled with a contact plug.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view showing a portion of a typical DRAM cell arrayregion; and

FIGS. 2-7 are cross-sectional views for illustrating preferred methodsof forming self-aligned contact structure according to the presentinvention along the line I—I of the FIG. 1.

DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. It will also be understood that when a layer is referred to asbeing “on” another layer or substrate, it can be directly on the otherlayer or substrate, or intervening layers may also be present. Likenumbers refer to like elements throughout.

FIG. 1 is a top plan view of a portion of a typical DRAM cell arrayregion.

Referring to FIG. 1, an active region 2 is defined at a predeterminedregion of a P-type semiconductor substrate and a pair of word lines 4 aand 4 b run over the active region 2 in parallel. An isolation layer isformed at an outside region of the active region 2. The active region 2between the pair of word lines 4 a and 4 b corresponds to a common drainregion 6 d doped with n-type impurities. The active regions 2 at bothside of the common drain region 6 d are a first source region 6 s′ andsecond source region 6 s″, respectively,

A first storage node pad 10 a, (e.g., a first pad plug) is disposed onthe first source region 6 s′ and (the first storage node pad 10 a) iselectrically connected to the first source region 6 s′. Similarly, asecond storage node pad 10 b, (e.g., a second pad plug) is disposed onthe second source region 6 s″ and (the second storage node pad 10 b) iselectrically connected to the second source region 6 s″. Also, a bitline pad 10 d is disposed on the common drain region 6 d and iselectrically connected to the common drain region 6 d. The bit line pad10 d comprises a protrusion extended toward one side of the activeregion 2. First and second bit lines 19 are disposed across the pair ofword lines 4 a and 4 b. The first bit line 19 is electrically connectedto the bit line pad 10 d through a bit line contact hole 14 exposing theprotrusion of the bit line pad 10 d. Like this, the second bit line 19is electrically connected to another bit line pad (not shown).

Now, the present invention will be described in detail with thereference drawings (FIGS. 2 to 7).

Referring to FIG. 2, preferred methods of forming integrated circuitdevices with self-aligned contact holes include a step of forming anisolation layer 2 a defining an active region (2 of FIG. 1) at apredetermined region of a P-type semiconductor substrate 1. Theisolation layer 2 a may be formed using conventional isolationtechniques such as trench isolation processes or LOCOS (local oxidationof silicon) processes. A pair of word lines (4 a and 4 b of FIG. 1) arethen formed across the active region. N-type impurities are implantedinto the active region using the word lines as an ion implantation mask,thereby forming source/drain regions (6 s′, 6 s″ and 6 d of FIG. 1). Alower inter-layer insulating layer 8 is formed on the entire surface ofthe resultant where the source/drain regions are formed. The lowerinter-layer insulating layer 8 may be formed of silicon oxide layer suchas borophosphosilicate glass (BPSG) layer, phosphosilicate glass (PSG)layer or undoped silicate glass (USG) layer.

A conventional photolithographically defined masking may then beperformed to form a pad contact hole 9 in the lower interlayerinsulating layer 8. This pad contact hole 9 exposes the source/drainregions. A blanket layer of polysilicon is then deposited on the lowerinterlayer insulating layer 8 and in the pad contact hole 9. Thisblanket layer of polysilicon may be a highly conductive polysiliconlayer having N-type dopants therein. The blanket layer of polysiliconmay then be planarized using the lower interlayer insulating layer 8 asa planarization stop layer. This planarization step results in theformation of a pad plugs (10 a, 10 b and 10 d of FIG. 1) which act ashighly conductive intermediate contacts to the underlying source/drainregions.

Referring to FIG. 3, an insulating layer 12 is formed on the lowerinterlayer insulating layer 8 and the pad plugs 10 a, 10 b and 10 d. Theinsulating layer 12 may be formed of silicon oxide layer such as hightemperature oxide (HTO) layer. The insulating layer 12 is patterned toform a bit line contact hole (14 of FIG. 1) exposing the bit line pad(10 d of FIG. 1). A conductive layer 19 and a protection layer 20 aresequentially formed on the substrate having the bit line contact hole14. The conductive layer 19 is preferably formed by sequentiallystacking a polysilicon layer 16 and a metal silicide layer 18, and theprotection layer 20 is preferably formed of a silicon oxide layer suchas a HTO layer. The metal silicide layer 18 may be formed of refractorymetal silicide layer such as tungsten silicide (WSi₂) layer and theprotection layer 20 may be formed of a silicon nitride layer. Thetungsten silicide (WSi₂) layer may be formed using a sputtering process.

Referring now to FIG. 4, the protection layer 20, the conductive layer19 and the insulating layer 12 is successively patterned using aphotolithographic process to form a plurality of interconnectionpatterns, (e.g., a first and a second bit line patterns 22), coveringthe bit line contact holes 14 and expose a portion of the lowerinterlayer insulating layer 8 and the pad plugs 10 a, 10 b and 10 d.These bit line patterns 22 may be formed as parallel stripes whichextend in a third dimension (not shown). The respective bit line pattern22 may comprise an insulating layer pattern 12 a, bit line 19 a andprotection layer pattern 20 a which are sequentially stacked. Here, therespective bit line 19 a may comprise a polysilicon pattern 16 a and atungsten silicide pattern 18 a which are sequentially stacked. As willbe understood by those skilled in the art, the use of tungsten silicideas a bit line material lowers the per unit length resistance of each bitline 19 a.

A blanket capping insulating layer 24 is then conformally deposited onthe lower interlayer insulating layer 8, the pad plugs 10 a, 10 b, 10 dand the bit line patterns 22, as illustrated. The capping insulatinglayer 24 is preferably formed of an insulating layer having a high wetetching selectivity with respect to an upper interlayer insulating layerto be formed in a subsequent process. In more detail, the cappinginsulating layer 24 is preferably formed of silicon nitride layer orsilicon oxynitride (SiON) layer having a thickness of 50 to 100 A. Arelatively thick upper interlayer insulating layer 26, filling gapregions between the bit line patterns 22, is then formed on the cappinginsulating layer 24. The upper interlayer insulating layer 26 maycomprise a material selected from the group consisting of undopedsilicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicateglass (PSG) and high temperature oxide (HTO).

Referring to FIG. 5A, a photoresist pattern 27 is formed on the upperinterlayer insulating layer 26 to selectively expose the upperinterlayer insulating layer 26 above the first and second pad plugs (10a, 10 b). Next, the exposed upper interlayer insulating layer 26 and thecapping insulating layer 24 are dry-etched in sequence using thephotoresist pattern 27 as an etching mask, thereby forming a relativelynarrow and deep contact hole, (e.g., a first contact hole 32) exposing afirst portion of the first pad plug 10 a. At this time, another firstcontact hole is also formed on the second pad plug (10 b of FIG. 1). Itis preferable that the dry etching process for forming the first contacthole 32 is performed using a conventional oxide etch recipe showing apoor etching selectivity respect to silicon nitride layer. In moredetail, the dry etching process for forming the first contact hole 32may be performed with a oxide etch recipe using CF4 gas or CHF3 gas.

The first contact hole 32 is preferably formed as a narrow hole in orderto reduce the likelihood that misalignment of the photoresist pattern 27will cause the underlying bit line patterns 22 to become exposed duringthe dry etching step. Such exposure of the bit line patterns 22 can leadto electrical bridging and other parasitic faults that may reducereliability and lifetimes of dynamic random access memory (DRAM) devicesformed in the active region.

FIG. 5B is a cross sectional view for illustrating another method offorming a first narrow contact hole.

Referring to FIG. 5B, as described in FIG. 5A, the photoresist pattern27 is formed on the upper interlayer insulating layer 26. Thephotoresist pattern 27 is then reflowed at a temperature of about 150 to200° C. to form a flowed photoresist pattern 27 a having a slopedsidewall. Accordingly, the exposed area of the upper interlayerinsulating layer 26 is reduced. The exposed upper interlayer insulatinglayer 26 and the capping insulating layer 24 are dry-etched in sequenceusing the flowed photoresist pattern 27 a as an etching mask to form arelatively narrow contact hole, e.g., a first narrow contact hole 32.

Alternatively, referring to FIG. 5C, in order to define the first narrowcontact hole 32, a hard mask layer is formed on the upper interlayerinsulating layer 26. The hard mask layer is preferably formed of a denseoxide layer such as high temperature oxide (HTO) layer. The hard masklayer is patterned using conventional techniques to form a mask pattern28 having a preliminary contact hole therein exposing a predeterminedregion of the upper interlayer insulating layer 26. Conventionalsidewall spacer technology is then used to form a mask spacer 30 on thesidewall of the mask pattern 28. The mask spacer 30 is preferably formedof the same material as the mask pattern 28.

The mask spacer 30 narrows the effective width of the preliminarycontact hole and thereby reduces the likelihood that a subsequentlyperformed etching step to expose the first and second pad plug 10 a and10 b will result in the inadvertent exposure of the bit line patterns22. In other words, the mask spacer 30 can be used advantageously toreduce the size of the preliminary contact hole and thereby increaseprocess reliability in the event that photolithographic misalignmenterrors occur when the mask layer is patterned. Next, the upperinterlayer insulating layer 26 and the capping layer 24 are dry-etchedin sequence using the mask pattern 28 and the mask spacer 30 as etchingmasks and thereby form a first narrow contact hole 32 exposing firstportions of the first and second pad plugs 10 a and 10 b. At this time,the mask pattern 28 and the mask spacer 30 are also etched. Therefore,the mask pattern 28 and the mask spacer 30 may be removed duringformation of the first contact hole 32.

Referring now to FIG. 6, after removing the photoresist pattern 27 ofFIG. 5A or the reflowed photoresist pattern 27 a of FIG. 5B, a wetetching step is performed to widen the first contact hole 32 in aself-aligned manner and thereby form a second contact hole 32 a. At thistime, the upper interlayer insulating layer 26 is isotropically etchedso that the upper surface thereof is lowered. Thus, an upper interlayerinsulating layer 26 a having a reduced thickness is formed. It ispreferable that the wet etching step is performed until the cappinginsulating layer 24 on the sidewalls of the bit line patterns 22 isexposed. In particular, the wet etching step is preferably performedusing an etchant that selectively etches the upper interlayer insulatinglayer 26 at a significantly faster rate than the capping insulatinglayer 24. In the event the capping insulating layer 24 and the upperinterlayer insulating layer 26 are formed of silicon nitride and siliconoxide, respectively, hydrofluoric acid (HF) or buffered oxide etchant(BOE) is preferable used as the wet etchant.

During this wet etching step, the capping insulating layer 24 is used asan etch stop layer (i.e., a protective layer for the sidewalls of thebit line patterns 22). By using the capping insulating layer 24 as anetch stop layer, the second contact hole 32 a can be formed in aself-aligned manner (with respect to the bit line patterns 22) even ifsome misalignment of the first contact hole 32 is present. Subsequently,an oxide spacer 34 having a width of about 500A is formed on a sidewallof the second contact hole 32 a in a conventional manner. At this time,a portion of the capping insulating layer 24 (i.e. a protrusion 24 a)may be exposed on the bottom of the second contact hole 32 a. The oxidespacer 34 is preferably formed of insulating layer having a lowdielectric constant, for example, a silicon oxide layer such as hightemperature oxide (HTO). The width of the oxide spacer 34 can bedetermined appropriately according to a width of the second contact hole32 a.

Referring to FIG. 7, the protrusion 24 a of the capping insulating layer24 is dry-etched to expose a second portion greater than the firstportion of the pad plugs 10 a and 10 b. In case the oxide spacer 34 isformed using the etching recipe described in FIGS. 5A to 5C (i.e., theetching recipe for forming the first contact hole 32), the protrusion 24a of the capping insulating layer 24 may be easily removed withoutapplying any additive etching process. Thus, the step of forming theoxide spacer 34 and the step of etching the protrusion 24 a can beperformed with in-situ process using one etching recipe. As a result, anextension 24 b of the capping insulating layer 24 exists under the oxidespacer 34.

Meanwhile, according to the above mentioned, even if the pad plugs 10 aand 10 b are not exposed completely during the formation of the firstcontact hole 32, the second contact hole 32 a exposing the secondportions of the pad plugs 10 a and 10 b can be formed. This is becausethe capping insulating layer 24 on the bottom of the second contact hole32 a may be completely exposed during the wet etch process for formingthe second contact hole 32 a and the exposed capping insulating layer 24can be easily removed during the step of forming the oxide spacer 34. Asa result, process margin of the etch step for forming the first contacthole 32 can be increased.

In addition, an etch stop spacer 36 may further formed on the innersidewall of the oxide spacer 34. In more detail, a thin etch stop layerhaving a thickness of 50 to 100A is conformally formed on the entiresurface of the structure of FIG. 6, and the etch stop layer isanisotropically etched to form the etch stop spacer 36. The etch stoplayer is preferably formed of an insulating layer having a high etchselectivity respect to the oxide wet etchant, for example, siliconnitride or silicon oxynitride. Alternatively, the protrusion 24 a may beetched in sequence after formation of the etch stop spacer 34.

A conductive layer such as doped polysilicon layer is then formed on theentire surface of the etch stop spacer 36. Here, a wet cleaning processmay be performed in order to remove a native oxide layer and/orcontaminants on the exposed pad plugs 10 a and 10 b prior to formationof the conductive layer filling the second contact hole 32 a. The wetcleaning process is typically performed using a mixture of ammoniahydroxide (NH4OH), hydro-peroxide (H2O2) and de-ionized water, andbuffered oxide etchant (BOE). At this time, the etch stop spacer 36which may be formed of silicon nitride or silicon oxynitride shows highetch selectivity respect to the wet cleaning solutions. Thus, the oxidespacer 34 is safely protected by the etch stop spacer 36.

Next, the conductive layer is etched-back until the upper surface of theupper interlayer insulating layer 26 a is exposed, to thereby form acontact plug 38 in the second contact hole 32 a.

Referring still to FIG. 7, the capping insulating layer 24, the oxidespacer 34 and the etch stop spacer 36 are interposed between the contactplug 38 and the bit line patterns 22. Here, even if the cappinginsulating layer 24 and the etch stop spacer 36 are formed of a verythin silicon nitride or silicon oxynitride having a thickness of 50 to100A, a self-aligned contact hole can be formed without damaging the bitline patterns 22. Accordingly, it is possible to remarkably reduce aparasitic capacitance between the contact plug 38 and the bit lines 19 aby forming the oxide spacer 34 having an adequate width therebetween.Also, it is easy to reduce a contact resistance between the contact plug38 and the pad plugs 10 a and 10 b by maximizing the contact areatherebetween.

As described above, methods of the present invention can be used toprevent bit lines from being exposed by self-aligned contact holes.Also, it can improve the alignment margin of the photolithographyprocess for forming the first contact hole. Therefore, it can realizethe reliable self-aligned contact structure. In addition, it can reducethe parasitic capacitance between the contact plug and the bit lines byforming the reliable oxide spacer therebetween.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A method of forming an integrated circuit device, comprising thesteps of: forming a microelectronic structure on a substrate; covering asidewall of the microelectronic structure and a portion of the substratewith a first electrically insulating layer comprising a first material;then covering the microelectronic structure and the first electricallyinsulating layer with a second electrically insulating layer comprisinga second material different from the first material; etching the secondelectrically insulating layer and the first electrically insulatinglayer in sequence to define a contact hole therein that exposes thesubstrate; and widening the contact hole to expose the firstelectrically insulating layer by wet etching sidewalls of the contacthole using an etchant that etches the second material faster than thefirst material.
 2. The method of claim 1, wherein said widening step isfollowed by the steps of: forming a sidewall insulating spacer on asidewall of the contact hole; and then etching a portion of the firstelectrically insulating layer extending opposite the substrate, usingthe sidewall insulating spacer as an etching mask.
 3. The method ofclaim 2, wherein the substrate comprises a polysilicon conductive plugtherein; and wherein said step of etching the second electricallyinsulating layer and the first electrically insulating layer in sequencecomprises etching the first electrically insulating layer to expose theconductive plug.
 4. The method of claim 3, wherein the firstelectrically insulating layer comprises silicon nitride; and wherein thesecond electrically insulating layer comprises silicon dioxide.
 5. Themethod of claim 3, wherein said dry etching step comprises dry etchingthe second electrically insulating and the first electrically insulatinglayer in sequence to expose the conductive plug.
 6. The method of claim1, wherein said step of etching the second electrically insulating layerand the first electrically insulating layer in sequence comprises dryetching the second electrically insulating and the first electricallyinsulating layer in sequence.
 7. A method of forming an integratedcircuit memory device, comprising the steps of: forming an electricallyconductive bit line on a substrate having a first conductive plugtherein extending to a surface thereof; covering the bit line and thefirst conductive plug with a silicon nitride capping layer; thencovering the bit line and the silicon nitride capping layer with anelectrically insulating oxide layer; dry etching the electricallyinsulating oxide layer and the silicon nitride capping layer in sequenceto define a contact hole therein that exposes the first conductive plugat the surface; and widening the contact hole to expose the siliconnitride capping layer by wet etching sidewalls of the contact hole usingan etchant that etches the electrically insulating oxide layer at afaster rate than the silicon nitride capping layer.
 8. The method ofclaim 7, wherein said widening step is followed by the steps of: formingan oxide spacer on a sidewall of the contact hole; and then wet etchinga portion of the silicon nitride capping extending opposite the firstconductive plug, using the oxide as an etching mask.
 9. The method ofclaim 8, wherein said step of wet etching a portion of the siliconnitride capping layer is followed by the step of forming a secondconductive plug that extends in the contact hole and ohmically contactsthe first conductive plug.
 10. The method of claim 9, wherein said stepof forming an electrically conductive bit line comprises forming anelectrically conductive bit line as a composite of a polysiliconconductive layer and a tungsten silicide layer on an upper surface ofthe polysilicon conductive layer.
 11. The method of claim 7, whereinsaid step of forming an electrically conductive bit line comprisesforming an electrically conductive bit line as a composite of apolysilicon conductive layer and a tungsten silicide layer on an uppersurface of the polysilicon conductive layer.
 12. A method of forming anintegrated circuit memory device, comprising the steps of: forming afirst interlayer insulating layer on a semiconductor substrate; forminga first contact hole in the first interlayer insulating layer; forming afirst conductive plug in the first contact hole; forming first andsecond bit lines at adjacent locations on an upper surface of the firstinterlayer insulating layer; forming a capping layer that covers thefirst conductive plug and the first and second bit lines; forming asecond interlayer insulating layer on the capping layer; etching thesecond interlayer insulating layer and the capping layer in sequence todefine a second contact hole that exposes a first portion of the firstconductive plug; widening the second contact hole by selectively etchingthe sidewalls of the second contact hole with an etchant that etches thesecond interlayer insulating layer at a faster rate than the cappinglayer; then forming a sidewall spacer on the sidewall of the secondcontact hole; and etching the capping layer to expose a second portionof the first conductive plug that is greater than the first portion,using the sidewall spacer as an etching mask.
 13. The method of claim12, wherein the first and second interlayer insulating layers comprisesilicon dioxide; and wherein the capping layer comprises siliconnitride.
 14. The method of claim 12, wherein said step of etching thesecond interlayer insulating layer is preceded by the steps of: forminga masking layer having a pilot hole therein, on the second interlayerinsulating layer; and narrowing the pilot hole by forming a pilot holespacer on a sidewall of the first pilot hole.
 15. The method of claim14, wherein said step of etching the second interlayer insulating layercomprises dry etching the second interlayer insulating layer through thenarrowed pilot hole.
 16. The method of claim 15, wherein the secondinterlayer insulating layer comprises a material selected from the groupconsisting of undoped silicate glass (USG), borophosphosilicate glass(BPSG), phosphosilicate glass (PSG) and high temperature oxide (HTO).17. The method of claim 16, wherein the capping layer comprises amaterial selected from the group consisting of silicon nitride, nitridedoxide and oxynitride.
 18. The method of claim 12, wherein the secondinterlayer insulating layer comprises a material selected from the groupconsisting of undoped silicate glass (USG), borophosphosilicate glass(BPSG), phosphosilicate glass (PSG) and high temperature oxide (HTO).19. The method of claim 18, wherein the capping layer comprises amaterial selected from the group consisting of silicon nitride, nitrideoxide and oxynitride.